1. Technical Field of the Invention
This disclosure relates to a circuit with fuses and a semiconductor device having the same circuit, and more particularly to a circuit with make link fuses or break link fuses and a semiconductor device including the same circuit.
2. Description of the Related Art
Generally, fuses are incorporated into a semiconductor device to allow circuits in the semiconductor devices to be selectively repaired or programmed after the semiconductor devices are fabricated. Such fuses are classified as “break link” fuses or “make link” fuses, depending on their function.
Typically, a break link fuse is fabricated by forming a conductive strip line such as polysilicon strip line, and the conductive strip line is split into two pieces by being cut out by a laser beam when the break link fuse is programmed after fabrication. On the other hand, the make link fuse includes two conductive strip lines which are stacked in a vertical direction and insulated from each other by an insulation layer that is interposed between the two conductive strips lines before the fuse is programmed. The two conductive lines are electrically connected through the interposing insulating layer after the make link fuse is programmed after fabrication.
That is, the break link fuse is in an electrically conductive status just when it is fabricated and programming of the break line fuse is accomplished by cutting the electrical connection across the break link fuse, but the make link fuse is not in an electrically conductive status when it is fabricated and programming of the make link fuse is accomplished by electrically connecting two electrically insulated conductive lines to each other.
The break link fuse is disadvantageous in that leakage current flows if the break link fuse is not completely cut off when the break line fuse is programmed.
The make link fuse is disadvantageous in that electrical conduction between the two conductive lines is easily apt to be cut off by even a small amount of current due to electro-migration since the two conductive lines are barely connected when the make link fuse is programmed. Accordingly, the connection between the two conductive lines is not cut off only if no current flows when the two conductive lines of the make link fuse are connected.
A conventional circuit with fuses is problematic because a power supply voltage and a ground voltage are usually applied to both ends of the respective break link fuses at an enable of the circuit with fuses, so leakage current flows through the fuses before the break link fuse is completely cut off. Furthermore, in the case of make link fuses, connected make link fuses may be cut off due to such leakage current.
FIG. 1 illustrates a circuit with fuses in accordance with an example of the conventional art. Referring to FIG. 1, a circuit with fuses in accordance with the conventional art includes a PMOS transistor P1, NMOS transistors N1 and N2, a fuse F1, and inverters I1 and I2.
The operation of the circuit shown in FIG. 1 is described below.
First, a control signal CON is generated upon detection of power-up of a system. The control signal CON may be a pulse signal generated internally or externally, or the control signal CON may be a signal having a logic “low” level at an initial stage that transitions to a logic “high” level upon detection of power-up, maintaining the logic “high” level ever after.
Assuming that the fuse F1 is a break link fuse, the fuse F1 is cut off, and the control signal CON is the pulse signal, if the control signal CON transitions from a logic “low” level to a logic “high” level, the PMOS transistor P1 is turned off and the NMOS transistor N1 is turned on, so that a node n1 becomes a ground voltage. The inverters I1 and I2 buffer a signal of the node n1 and generate a signal MS at a ground voltage level. The NMOS transistor N2 is turned on in response to a signal of a node N2 and brings the node 1 to a ground voltage level.
After that, if the control signal CON transitions from logic “high” level to logic “low” level, the PMOS transistor P1 is turned on and the NMOS transistor N1 is turned off. At this time, since the break link fuse F1 is cut off, the circuit outputs a signal that is latched by the inverter I1 and the NMOS transistor N2. That is, the signal MS is generated at a ground voltage level.
At this time, if the break link fuse F1 is not completely cut off, when the control signal CON transitions from logic “low” level to logic “high” level or vice versa, the PMOS transistor P1 and the NMOS transistor N1 are turned on at the same time. As a result, leakage current may flow through the break link fuse F1.
Assuming that the fuse F1 is a make link fuse, the conductive lines in the fuse F1 are electrically connected (programmed), and the control signal CON is a pulse signal, if the control signal CON transitions from a logic “low” level to a logic “high” level, the node n1 becomes a ground voltage, and the inverters I1 and I2 buffer a signal of the node n1 and generate the signal MS at a ground voltage level in the same manner as the break link fuse.
After that, if the control signal CON transitions from a logic “high” level to a logic “low” level, the PMOS transistor P1 is turned on and the NMOS transistor N1 is turned off. At this time, since the make link fuse F1 is electrically connected, the node n1 becomes a power supply voltage level. The inverters I1 and I2 buffer the signal of the node n1 and generate the signal MS of a power supply voltage level. The NMOS transistor N2 is turned off in response to the node n2 of a ground voltage level.
However, when the control signal CON transitions from a logic “low” level to a logic “high” level or vice versa, the PMOS transistor P1 and the NMOS transistor N1 are turned on at the same time. This causes current flow through the make link fuse F1, such that the make link fuse F1 may be electrically cut off.
FIG. 2 illustrates a conventional redundancy address decoding circuit that includes fuses. As shown in FIG. 2, a conventional redundancy address decoding circuit includes PMOS transistors P21, P22, . . . , P2n, NMOS transistors N31, N32, . . . ,N3n, fuses F21, F22, . . . , F2n, and an AND gate AND1.
The operation of the circuit shown in FIG. 2 is described below.
If a memory cell accessed using a decoding address DA1, DA2, . . . , DAn with logic values “1, . . . ,1,0”, respectively, fails and the memory cell needs to be repaired, a logic “high” level of the signal MS is generated from the circuit shown in FIG. 1. Fuses F21–F2n are programmed in accordance with the decoding address “1, . . . ,1,0”, and a redundancy address decoding signal PRE is generated.
If the fuses F21–F2n are break link fuses, only the fuse F2n is cut off to program the decoding address “1, . . . ,1,0”. If the fuses F21–F2n are make link fuses, the fuses F21–F21(n−1) are connected to program the decoding address “1, . . . ,1,0”. Then, when “1, . . . ,1,0” of the decoding address DA1, DA2, . . . , DAn is input, a redundancy enable signal PRE of logic “high” level is generated.
However, in the circuit shown in FIG. 2, if the break link fuse F2n is not completely cut off, the PMOS transistor P2n and the NMOS transistor N3n are turned on at the same time when the signal MS transitions from logic “low” level to logic “high” level, or transitions from logic “high” level to logic “low” level, so that current flows through the break link fuse F2n. 
Furthermore, in the case where the fuses F21–F2n are make link fuses, when the redundancy enable signal MS transitions from logic “low” level to logic “high” level or transitions from logic “high” level to logic “low” level, all the PMOS transistors P21–P2(n−1) and all the NMOS transistors N31–N3(n−1) are turned on at the same time and current flows through the electrically connected make link fuses F21–F2(n−1), so that the electrically connected make link fuses may be cut off.
When the control signal CON transitions from logic “low” level to logic “high” level, the same leakage current problem described above occurs.
Embodiments of the invention address these and other disadvantages of the conventional art.